I am currently working as an Engineer at Tenstorrent, focusing on RISC-V hardware design verification. I completed my undergraduate in Electrical Engineering with a minor in Computing at the Indian Institute of Technology (IIT) Madras, India.
My interests broadly encompass the fields of Hardware Accelerators, Computer Architecture, Hardware-Software Co-design, and FPGA and ASIC Architecture, RISC-V, and VLSI design.
I worked as a Student Developer for the Google Summer of Code 2021 program, where I focused on Digital Design and FPGAs, creating virtual FPGA labs using Makerchip. Additionally, I worked with Prof. Nitin Chandrachoodan at IIT Madras on providing a harness-based framework for Rapid FPGA Hardware Prototyping and support for Cloud FPGAs. I also did a research internship at the Georgia Institute of Technology under Prof. Cong "Callie" Hao, working on enabling Approximate Computing on Graph Neural Networks. Furthermore, I gained industry experience during a summer internship with Qualcomm, working with the modem hardware team. I was also a core team member of the Electronics Club at IIT Madras. I led a group of electronics enthusiasts exploring various electronics domains and managing club projects, sessions, and activities.
My Bachelor Thesis, focused on Binary Neural Network Inference on FPGAs under the guidance of Prof. Nitin Chandrachoodan and in collaboration with KLA Advanced Computing Labs, Chennai. I am also an open-source contributor and have conducted several workshops on FPGAs and embedded microcontrollers.
I love to play Basketball and carrom.
- Python
- C/C++
- Assembly(ARM, RISC-V)
- HTML
- CSS
- JavaScript
- Tcl
- Bash
- Verilog
- TL-Verilog
- SystemVerilog
- Bluespec SystemVerilog
- Xilinx Vivado, Vitis
- PYNQ
- ChampSim
- Cachegrind
- LT-Spice
- Arduino
- PyTorch
- HLS4ML
- cocotb
Framework that provides a ready-to-use harness for testing user designs on Xilinx ZYNQ FPGAs
Online simulator to visualize FPGA and their peripheral outputs using the Visualization feature in the Makerchip platform, thereby mimicking the physical lab experience
Custom Data single core Prefetcher algorithm simulated using ChampSim microarchitectural simulator.
High-performance Bitonic Parallel sorting algorithm in Verilog HDL with a reconfigurable number of elements and bitwidth.
Circuit solver web application in JavaScript that avoids manually solving complex circuits with controlled sources. Implemented using draw2d.js.
Implemented RISC-V Bit Manipulation extension for RV32 and RV64 in Bluespec SystemVerilog. Simulated the design using Verilator and cocotb is used for writing test benches and verification.
Mandelbrot Fractal Generation acceleration in FPGA by designing AXI Stream IP design in Vitis HLS. Xilinx PYNQ framework is used to interact between the PS and PL of the PYNQ-Z2 FPGA.
Standard and two security-enhanced modified 128bit AES encryption acceleration by designing custom AXI-Lite IPs in Vivado and compare the performance.
5-stage pipelined 32-bit RISC-V ISA processor design in Transaction-Level Verilog (TL-Verilog). Incorporated Hazard-detection and Data forwarding units.
Given a list of random wikipedia pages link, the task is to crawl to Philosophy page with web scrapping using python.
This website uses the template by Brittany Chiang. Forked from here.